PSoC4100S
Overview
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex™-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
- Automotive Electronics Council (AEC) AEC-Q100 Qualified
- 32-bit MCU Subsystem ❐ 48-MHz Arm Cortex-M0+ CPU ❐ Up to 128 KB of flash with Read Accelerator ❐ Up to 16 KB of SRAM ❐ 8-channel DMA engine
- Programmable Analog ❐ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode. ❐ 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averaging ❐ Single-slope 10-bit ADC function provided by a capacitance sensing block ❐ Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin ❐ Two low-power comparators that operate in Deep Sleep low-power mode
- Programmable Digital ❐ Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
- Low-Power 1.71 V to 5.5 V Operation ❐ Deep Sleep mode with operational analog and 2.5 A digital system current
- Capacitive Sensing ❐ Cypress CapSense Sigma-
