S25FS256S
Overview
- Density - S25FS128S-128 Mbits (16 Mbytes) - S25FS256S-256 Mbits (32 Mbytes)
- Serial Peripheral Interface (SPI) - SPI Clock polarity and phase modes 0 and 3 - Double Data Rate (DDR) option - Extended Addressing: 24- or 32-bit address options - Serial Command subset and footprint compatible with S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families - Multi I/O Command subset and footprint compatible with S25FL-P, and S25FL-S SPI families
- Read - Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O - Modes: Burst Wrap, Continuous (XIP), QPI - Serial Flash Discoverable Parameters (SFDP) and Common Flash Interface (CFI), for configuration information
- Program - 256- or 512-byte Page Programming buffer - Program suspend and resume
- Erase - Hybrid sector option - Physical set of eight 4-kbyte sectors and one 32-kbyte sector at the top or bottom of address space with all remaining sectors of 64 kbytes - Uniform sector option - Uniform 64-kbyte or 256-kbyte blocks for software compatibility with higher density and future devices - Erase suspend and resume - Erase status evaluation - 100,000 Program-Erase Cycles on any sector, minimum - 20 Year Data Retention, typical
- Security Features - One-Time Program (OTP) array of 1024 bytes - Block Protection: - Status Register bits to control protection against program or erase of a contiguous range of sectors - Hardware and software control options - Advanced Sector Protection (ASP) - Individual sector protection controlled by boot code or password - Option for password control of read access
- Technology - Spansion 65 nm MirrorBit Technology with Eclipse™ Architecture
- Supply Voltage - 1.7V to 2.0V
- Temperature Range - Industrial (0°C to +85°C) - Industrial Plus (-40°C to +105°C)
- Packages (All Pb-Free) - 8-lead SOIC 2
