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S70FL01GS - 1 Gbit (128 Mbyte) 3.0V SPI Flash

General Description

This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die.

For detailed specifications, refer to the discrete die datasheet provided in the Affected Documents/Related Documents table.

Key Features

  • CMOS 3.0V Core.
  • Serial Peripheral Interface (SPI) with Multi-I/O.
  • SPI Clock polarity and phase modes 0 and 3.
  • Double Data Rate (DDR) option.
  • Extended Addressing: 32-bit address.
  • Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families.
  • Multi I/O Command set and footprint compatible with S25FL-P SPI family.
  • READ Commands.
  • Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR.
  • AutoBoo.

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Other Datasheets by Cypress (now Infineon)

Part Number Description
S70GL02GP 2 Gbit / 3V Page Mode S70GL-P MirrorBit Flash
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S70GL02GT 2-Gbit (256-Mbyte) 3.0V Flash Memory

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
S70FL01GS 1 Gbit (128 Mbyte) 3.0V SPI Flash Features  CMOS 3.0V Core  Serial Peripheral Interface (SPI) with Multi-I/O – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 32-bit address – Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families – Multi I/O Command set and footprint compatible with S25FL-P SPI family  READ Commands – Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR – AutoBoot – power up or reset and execute a Normal or Quad read command automatically at a preselected address – Common Flash Interface (CFI) data for configuration information  Programming (1.5 Mbytes/s) – 512-byte Page Programming buffer – Quad-Input Page Programming (QPP) for slow clock systems  Erase (0.