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S71KS512SC0 - HyperFlash and HyperRAM Multi-Chip Package

Description

3 HyperBus MCP Family with HyperFlash and HyperRAM 3 HyperBus MCP 3 V Signal Descriptions 4 HyperBus MCP Block Diagram 5 Physical Interface 6 HyperBus MCP FBGA 24-Ball, 5x5 Array Footprint 6 Physical Diagram 7 Electrical Specifications 8 Absolute Maximum Ratings 8 DC Characteristi

Features

  • operation, and ordering options of the related memories have been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document modifies any information on the same topics established by the documents listed in Table 1 and should be used in conjunction with those documents. This document may also contain information that was not previously covered by the listed documents. The information is intended for hardware system designers and sof.

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Other Datasheets by Cypress (Infineon)

Part Number Description
S71KL256SC0 HyperFlash and HyperRAM Multi-Chip Package
S71KL512SC0 HyperFlash and HyperRAM Multi-Chip Package

Full PDF Text Transcription

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SUPPLEMENT S71KS512SC0 S71KL256SC0 S71KL512SC0 HyperFlash™ and HyperRAM™ Multi-Chip Package 1.8V/3V HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V Distinctive Characteristics ■ HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP) ❐ 1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KS512SC0) ❐ 3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM (S71KL512SC0) ❐ 3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM (S71KL256SC0) ❐ FBGA 24-ball, 6  8  1.0 mm package ■ HyperBus Interface ❐ 1.8V I/O, 12 bus signals • Differential clock (CK/CK#) ❐ 3.
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