VIC068 Datasheet | Cypress

Features - plete VMEbus interface controller and arbiter - 58 internal registers provide configuration control and status of VMEbus and local operations - Drives arbitration, interrupt, address modifier utility, strobe, address lines A07 through A01 and data lines D07 through D00 directly, and provides signals for control logic to drive remaining address and data lines - Direct connection to 68xxx family and mappable to non-68xxx processors plete master/slave capability - - Supports read, write, write posting, and block transfers - Acmodates VMEbus timing requirements with internal digital delay line (1⁄ 2-clock granularity) - Programmable metastability delay - Programmable data acquisition delays - Provides timeout timers for local bus and VMEbus transactions Interleaved block transfers over VMEbus - - Acts as DMA master on local bus - Programmable burst count, transfer length, and interleaved period interval - Supports local module-based DMA Arbitration support - - Supports single-level, priority and round robin arbitration - Supports fair request option as requester - Interrupt support - plete support for the VMEbus interrupts: interrupter and interrupt handler - Seven local interrupt lines - 8-level interrupt priority encode - Total of 29 interrupts mapped through the VIC068A - Miscellaneous features - Refresh option for local DRAM - Four broadcast location monitors - Four module-specific location monitors - Eight interprocessor munications registers - PGA or QFP packages - patible with IEEE Specification 1014, Rev. C - Supports RMC operations - See the VMEbus Interface Handbook for more information Functional Description The VMEbus interface controller (VIC068A) is a single chip designed to minimize the cost and board area requirements and to maximize performance of the VMEbus interface of a VMEbus master/slave module. This can be implemented on VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The VIC068A performs all VMEbus system controller...