W152 Overview
The output signals QA0:3 through QB0:3 will be synchronized to this signal unless the device is programmed to bypass the PLL. When programmed to zero delay buffer mode, this input must be fed by one of the outputs (QA0:3 or QB0:3) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then...
W152 Key Features
- Spread Aware™-designed to work with SSFTG reference signals
- Two banks of four outputs each
- Configuration options to halve, double, or quadruple the reference frequency refer to Table 1 to determine the specific
- Outputs may be three-stated
- Available in 16-pin SOIC package
- Extra strength output drive available (-11/-12 versions)
- Contact factory for availability information on 16-pin TSSOP Output to Output Skew: Between Banks
- 215 ps Output to Output Skew: Within Banks (Refer to Figure 4)
- 100 ps Total Timing Budget Impact
- 555 ps Max. Phase Error Variation
