W232 Overview
Output signals Q0:9 will be synchronized to this signal. This input must be fed by one of the outputs (typically FBOUT) to ensure proper functionality. If the trace between FBIN and FBOUT is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations will be synchronized to the CLK signal input.
W232 Key Features
- Well suited to both 100- and 133-MHz designs Ten/Eleven LVCMOS/LVTTL outputs 3.3V power supply Available in 24-pin TSSOP
- 3.3V±10% Operating Range
- 25 MHz < fOUT < 140 MHz Cycle-to-Cycle Jitter
- <150 ps Output to Output Skew
- <100 ps Phase Error Jitter
- <125 ps Static Phase Error
- <150 ps