Datasheet Details
| Part number | W40S11-23 |
|---|---|
| Manufacturer | Cypress (now Infineon) |
| File Size | 124.01 KB |
| Description | Clock Buffer/Driver |
| Datasheet |
 W40S11-23 Datasheet
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General Description
SDRAM Outputs: Provides buffered copy of BUF_IN.
The propagation delay from a rising input edge to a rising output edge is 1 to 5 ns.
All outputs are skew controlled to within ± 250 ps of each other.
Key Features
- Thirteen skew-controlled CMOS clock outputs (SDRAM0:12).
- Supports three SDRAM DIMMs.
- Ideal for high-performance systems designed around Intel’s latest chip set.
- I2C serial configuration interface.
- Clock Skew between any two outputs is less than 250 ps.
- 1- to 5-ns propagation delay.
- DC to 133-MHz operation.
- Single 3.3V supply voltage.
- Low power CMOS design packaged in a 28-pin, 300-mil SOIC (Small Outline Integrated.