CY7C1370CV25 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture Datasheet

CY7C1370CV25 Key Features

Pin-patible and functionally equivalent to ZBT™
Supports 250-MHz bus operations with zero wait states
Available speed grades are 250, 225, 200 and 167 MHz
Internally self-timed output buffer control to eliminate the need to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
Single 2.5V power supply
Fast clock-to-output times
2.6 ns (for 250-MHz device)
2.8 ns (for 225-MHz device)

Part Number	Description
CY7C1370C	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1370D	18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM
CY7C1371C	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
CY7C1371S	18-Mbit (512K x 36) Flow-Through SRAM
CY7C1372C	512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture