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CY7C4804V25 - 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching

Description

The CY7C480XV25 family of FIFOs is comprised of high-speed, low-power, CMOS Synchronous (clocked) FIFO memories, meaning both independent ports employ a synchronous interface.

All data transfers through a port are gated to the LOW-to-HIGH transition of the clock on either port by the enable signal.

Features

  • High-speed, low-power, unidirectional, First-in First-out (FIFO) memories with bus-matching capabilities.
  • 64K × 80 (CY7C4808V25).
  • 16K × 80 (CY7C4806V25).
  • 4K × 80 (CY7C4804V25).
  • 2.5V ± 100 mV power supply.
  • All I/Os are 1.5V HSTL.
  • Individual clock frequency up to 200 MHz (5-ns Read/Write cycle times).
  • High-speed access with tA = 3.8 ns.
  • Bus matching on both ports: ×80, ×40, ×20, ×10.
  • Free-running CLKA and CL.

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Datasheet Details

Part number CY7C4804V25
Manufacturer Cypress (Infineon)
File Size 375.23 KB
Description 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching
Datasheet download datasheet CY7C4804V25 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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sure C025/0251 PRELIMINARY CY7C4808V25 CY7C4806V25 CY7C4804V25 2.5V 4K/16K/64K x 80 Unidirectional Synchronous FIFO with Bus Matching Features • High-speed, low-power, unidirectional, First-in First-out (FIFO) memories with bus-matching capabilities • 64K × 80 (CY7C4808V25) • 16K × 80 (CY7C4806V25) • 4K × 80 (CY7C4804V25) • 2.5V ± 100 mV power supply • All I/Os are 1.5V HSTL • Individual clock frequency up to 200 MHz (5-ns Read/Write cycle times) • High-speed access with tA = 3.8 ns • Bus matching on both ports: ×80, ×40, ×20, ×10 • Free-running CLKA and CLKB.
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