CYT3BB
Overview
CYT3BB/4BB is a family of Traveo™ II microcontrollers targeted at automotive systems such as high-end body-control units. CYT3BB/4BB has one or two Arm® Cortex®-M7 CPUs for primary processing, and an Arm Cortex-M0+ CPU for peripheral and security processing.
- CPU Subsystem ❐ One or two[1] 250-MHz 32-bit Arm Cortex-M7 CPUs, each with
- Single-cycle multiply
- Single/double-precision floating point unit (FPU)
- 16-KB data cache, 16-KB instruction cache
- Memory Protection Unit (MPU)
- 16-KB instruction and 16-KB data Tightly-Coupled Memories (TCM) ❐ 100-MHz 32-bit Arm Cortex M0+ CPU with
- MPU ❐ Inter-processor communication in hardware ❐ Three DMA controllers
- Peripheral DMA controller #0 (P-DMA0) with 100 channels
- Peripheral DMA controller #1 (P-DMA1) with 58 channels
- Memory DMA controller (M-DMA0) with 8 channels
