MB96F655 Datasheet | Cypress

Features Technology 0.18m CMOS - F2MC-16FX CPU - Optimized instruction set for controller applications (bit, byte, word and long-word data types, 23 different addressing modes, barrel shift, variety of pointers) - 8-byte instruction queue - Signed multiply (16-bit  16-bit) and divide (32-bit/16-bit) instructions available System clock - On-chip PLL clock multiplier (1 to 8, 1 when PLL stop) - 4MHz to 8MHz crystal oscillator (maximum frequency when using ceramic resonator depends on Q-factor) - Up to 8MHz external clock for devices with fast clock input feature - 32.768k Hz subsystem quartz clock - 100k Hz/2MHz internal RC clock for quick and safe startup, clock stop detection function, watchdog - Clock source selectable from mainclock oscillator, subclock oscillator and on-chip RC oscillator, independently for CPU and 2 clock domains of peripherals - The subclock oscillator is enabled by the Boot ROM program controlled by a configuration marker after a Power or External reset - Low Power Consumption - 13 operating modes (different Run, Sleep, Timer, Stop modes) On-chip voltage regulator Internal voltage regulator supports a wide MCU supply voltage range (Min=2.7V), offering low power consumption Low voltage detection function Reset is generated when supply voltage falls below programmable reference voltage Code Security Protects Flash Memory content from unintended read-out DMA Automatic transfer function independent of CPU, can be assigned freely to resources Interrupts - Fast Interrupt processing - 8 programmable priority levels - Non-Maskable Interrupt (NMI) - Supports CAN protocol version 2.0 part A and B - ISO16845 certified - Bit rates up to 1Mbps - 32 message objects - Each message object has its own identifier mask - Programmable FIFO mode (concatenation of message objects) - Maskable interrupt - Disabled Automatic Retransmission mode for Time Triggered CAN applications - Programmable loop-back mode for...