S27KL0642 - HyperRAM Self-Refresh DRAM

Description

4 HyperBus Interface 4 Product Overview 6 HyperBus Interface 6 Signal Description 7 Input/Output Summary 7 HyperBus Transaction Details 8 Command/Address Bit Assignments 8 Read Transactions 12 Write Transactions (Memory Array Write) 13 Write Transactions without Initial Latency (Register W

Features

Interface.
HyperBus Interface.
1.8 V / 3.0 V interface support.
Single-ended clock (CK) - 11 bus signals.
Optional differential clock (CK, CK#) - 12 bus signals.
Chip Select (CS#).
8-bit data bus (DQ[7:0]).
Hardware reset (RESET#).
Bidirectional Read-Write Data Strobe (RWDS).
Output at the start of all transactions to indicate refresh latency.
Output during read transactions as Read Data Strobe.
Input during write transactions as Write Data.

Cypress

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Datasheet Details

Part number	S27KL0642
Manufacturer	Cypress
File Size	1.17 MB
Description	HyperRAM Self-Refresh DRAM
Datasheet	S27KL0642 Datasheet
Additional preview pages of the S27KL0642 datasheet.

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S27KS0642 - HyperRAM Self-Refresh DRAM

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S27KL0642/S27KS0642 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM S27KL0642/S27KS0642, 3.0 V/1.8 V, 64 Mb (8 MB), HyperRAM Self-Refresh DRAM Features Interface ■ HyperBus Interface ■ 1.8 V / 3.

Published: Apr 15, 2020 |