Cypress Semiconductor W137
The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched on the rising edge of PCI_F.FEATURES
● Maximized EMI suppression using Cypress’s Spread Spectrum Technology● Two copies of CPU output
● Six copies of PCI output (Synchronous w/CPU output)
● One 48-MHz output for USB support
● One selectable 24-/48-MHz output
● Two Buffered copies of 14.318-MHz input reference signal
● Supports 100-MHz or 66-MHz CPU operation
● Power management control input pins
● Available in 28-pin SSOP (209 mils)
● SS function can be disabled
● See W40S11-02 for 2 SDRAM DIMM support PCI_F, PCI1:5 Output to Output Skew:........................ 500 ps PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps CPU to PCI Output Skew: ............... 1.5–4.0 ns (CPU Leads) Output Duty Cycle: .................................................... 45/55% PCI_F, PCI Edge Rate: .............................................. >1 V/ns CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#, PWR_DWN# all have a 250-kΩ pull-up resistor. Table 1. Pin Selectable Frequency SEL100/66# 0/1 0 1 OE 0 1 1 CPU HI-Z 66.6 MHz 100 MHz PCI HI-Z 33.3 33.3 Spread% Don’t Care See Table 2 See Table 2 Key Specifications Supply Voltages: ...................................