Cypress Semiconductor Z9972
The divider ratio for this output is set by FB_SEL(0:2). This output is used for system synchronization.| Part No. | Z9972 |
|---|---|
| Datasheet | Z9972 Download |
| Manufacturer |  Cypress Semiconductor |
| Description | 3.3V/ 125-MHz/ Multi-Output Zero Delay Buffer |
| Buy | Stock & Price |
FEATURES
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● Output frequency up to 125 MHz 12 clock outputs: frequency configurable 350 ps max output-to-output skew Configurable output disable Two reference clock inputs for dynamic toggling Oscillator or crystal reference input Spread Spectrum-compatible Glitch-free output clocks transitioning 3.3V power supply Pin-compatible with MPC972 Industrial temperature range: –40°C to +85°C 52-pin TQFP package Table 1. Frequency Table[1] VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVCO 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note: 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. Block Diagram XIN XOUT VCO_SEL PLL_EN REF_SEL D Q TCLK0 TCLK1 TCLK_SEL FB_IN D Q Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3 Pin Configuration SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO...
