CY7C63310 Datasheet

CY7C63310 Key Features

• 4 I/O pins with 3.3V logic levels
• Each 3.3V pin supports high-impedance input, internal pull up, open drain output or traditional CMOS output
• SPI serial munication
• Master or slave operation
• Configurable up to 4 Mbit/second transfers in the master mode
• Supports half duplex single data line mode for optical sensors
• 2-channel 8-bit or 1-channel 16-bit capture timer registers. Capture timer registers store both rising and falling edge
• Two registers each for two input pins
• Separate registers for rising and falling edge capture
• Simplifies interface to RF inputs for wireless