MB91461
Overview
- 32-bit RISC, load/store architecture, five-stage pipeline
- Maximum operating frequency : 80 MHz (oscillation frequency 20 MHz, 4 multiplier (PLL clock multiplication method))
- 16-bit fixed-length instructions (basic instructions)
- Instruction execution speed : 1 instruction per cycle
- Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions: Instructions suitable for embedded applications
- Function entry/exit instructions and register data multi load store instructions: Instructions supporting C language
- Register interlock function : Facilitating assembly-language coding
- Built-in multiplier with instruction-level support Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles
- Interrupt (PC/PS saving) : 6 cycles (16 priority levels)
- Harvard architecture enabling simultaneous execution of both program access and data access
