INS6310A Datasheet | DAPU

- 1:10 Ultra-Low Additive Jitter Differential Clock Buffer Features - Two banks with 5 differential outputs each - LVPECL、LVDS、HCSL or Hi-Z (selectable per bank) - LVPECL additive jitter with clock source at 122.88MHz - 40 fs RMS (10KHz to 1MHz) - 80 fs RMS (12KHz to 20MHz) - 3:1 Input Multiplexer - Two universal inputs operate up to 2.5GHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL or single-ended clocks - One crystal input accepts 10 to 40MHz crystal or single-ended clock - High PSRR: -65/-76d Bc (LVPECL/LVDS) at 156.25MHz - LVCMOS output with synchronous enable input - Pin-Controlled configuration - VDD core supply: 3.3V ±5% - 3 independent VDDO output supplies: 3.3V/2.5V ±5% - Industrial temperature range: -40°C to +85°C - Package: QFN48(7.0mm- 7.0mm- 0.75mm) - APPLICATIONS - High speed Clock distribution and level translation - - U Wireless BBU, RRU and Wired munication DAP Servers, puting, PCI Express (PCIe) confidential - Switches, Routers, Line Cards, Timing Cards FOR GENERAL DESCRIPTIONS for 普 昕 悦 The INS6310A is a high performance, versatility 10-output differential fanout buffer intended for high-frequency, lowjitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 5 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The INS6310A operates from a 3.3V core supply and 3 independent 3.3V/2.5V output supplies. Version： 1.2 DAPU Confidential Page： 1 /...