GENERAL DESCRIPTION
A phase-locked transmit clock is transmitte d in p arallel with the data streams ove r a fif th L VDS link. A a transmitter (DTC34LM85L) w ill inter-o perate w ith without any translation logic. Using a 8 5 MHz clock, the dat a throu ghputs is 297.5 Mbytes/sec. ▓ REVISED APR. 2009 FEATURES
▓ Wide frequency range : 20 to 85 MHz shift clock support Narrow bus (10 lines) reduces cable size ▓ Sing le 3.3V supply ▓ Po wer-Down Mode ▓ ▓ ▓ ▓ ▓ ▓ ▓ ▓ Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and SXGA Up to 297.5 Megabytes/sec bandwidth Up to 2.38 Gbps throughput 300mV swing LVDS devices for low EMI PLL requires no external components Low profile 56-lead TSSOP package (PB Free) Compatible with the National DS90C386, T hine THC63LVDF84A Falling/Rising edg e rec eiver (DT C34LF86L/LR86L) ▓ Comp atible with TIA/EIA-644 LVDS standard Block Diagram DTC34LF86L/DTC34LR86L CMOS/TTL OUTPUTS 8 RED LVDS - TO - TTL PARALLEL 8 LVDS DATA ( 140 TO 595Mbit/s On Each LVDS Channel ) GRN 8 BLU HSYNC VSYNC DE(Data Enable) CNTL RCLK+/(20MHz ~ 85MHz) PLL CLKOUT (20MHz ~ 85MHz) /PDN(Power Down) -1- DOESTEK Co., Ltd.
