DP3S1MX32PY5 Description
The DP3S1MX32PY5 is a 1M x 32 SRAM module that utilizes the new and innovative space saving TSOP stacking technology. The module is constructed of two 1M x 16 SRAM’ s that are configured as a 1M x 32.
DP3S1MX32PY5 Key Features
- Organizations Available: 1M x 32
- Access Times: 10-, 12, 15, 20ns
- 3.3 ±0.3-- Volt Power Requirement
- Fully Static Operation
- No clock or refresh required
- TTL-patible Inputs and Outputs
- 80-Pin Surface Mount LP-Stack ™
- A19 I/O0
- I/O31 CS WE OE BS0 BS1 BS2 BS3 VDD VSS NU. Address Inputs Data Input/Output Stack Enable Write Enable Output Enable Byte
- I/O7 Byte Select I/O8