PDU10256H Datasheet | Data Delay Devices

FEATURES - - - - - Digitally programmable in 128 delay steps Monotonic delay-versus-address variation Precise and stable delays Input & outputs fully 10KH-ECL interfaced & buffered Fits 48-pin DIP socket GND ENB 1 2 48 47 GND OUT data 3 ® delay devices, inc. PACKAGES N/C N/C OUT GND ENB N/C N/C N/C GND ENB N/C N/C N/C N/C N/C N/C N/C GND ENB IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 N/C N/C A2 A1 VEE A0 N/C A5 A4 VEE A3 N/C N/C N/C N/C N/C N/C A7 VEE A6 A0 VEE GND 7 8 9 42 41 40 A1 A2 GND PIN DESCRIPTIONS IN OUT A0-A7 ENB VEE GND Signal Input Signal Output Address Bits Output Enable -5 Volts Ground A3 VEE GND IN 15 16 17 19 34 33 32 A4 A5 GND PDU10256H-xx C5 SMD PDU10256H-xx MC5 Mil SMD A6 VEE 23 24 25 A7 PDU10256H-xx DIP PDU10256H-xx M Mil DIP FUNCTIONAL DESCRIPTION The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following formula: TDA = TD0 + TINC - A where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS - - - - - - - Total programmed delay tolerance: 5% or 2ns, whichever is greater Inherent delay (TD0): 12ns typical Setup time and propagation delay: Address to input setup (TAIS): 3.6ns Disable to output delay (TDISO): 1.7ns typical Operating temperature: 0° to 70° C Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VEE: -5VDC ± 5% Power Dissipation: 925mw typical (no load) Minimum pulse width: 16% of total delay DASH NUMBER...