Data Device BUS-61559
the BUS-61559 series contains dual low-power transceivers and encoder/decoders, complete BC/RT/MT protocol logic, memory management and interrupt logic, 8K x 16 of shared static RAM, and a direct, buffered interface to a host processor bus. The BUS-61559 includes a number of advanced features in support of MIL-STD-1553B Notice 2 and STANAG 3838. The memory management scheme for RT mode prevails an option for separation of broadcast data, in compliance with 1553B Notice 2.
| Part No. |
BUS-61559 |
| Datasheet |
BUS-61559
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| Manufacturer |
 Data Device |
| Description |
MIL-STD-1553 Bc-rt-mt Integrated Terminal |
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FEATURES
(AIM-HY’er) DESCRIPTION
DDC’s BUS-61559 series of Advanced Integrated Mux Hybrids with enhanced RT FEATURES
(AIM-HY’er) comprise a complete interface between a microprocessor and a MIL-STD-1553B Notice 2 bus, implementing Bus Controller (BC), Remote Terminal (RX, and Monitor Terminal (MT) modes. Packaged in a single 78-pin DIP or 82-pin flat package Other salient features of the BUS-61559 serve to provide the benefits of reduced board space requirements enhanced software flexibility, and reduced host processor overhead buffers to provide a direct interface to a host processor bus. Alternatively, the buffers may be operated in a fully transparent mode in order to interface to up to 64K words of external shared RAM and/or connect directly to a component set supporting the 20 MHz STANAG-3910 bus. A circular buffer option for RT message data blocks offloads the host processor for bulk data transfer applications. Another feature besides those listed to the right, is a transmitter inhibit control for the individual bus channels.
