Dense-Pac Microsystems DPS128C32BV3
The DPS128C32BV3 ‘’VERSA-STACK’’ module is a revolutionary new high speed memory subsystem using Dense-Pac Microsystems’ ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 4 Megabits of SRAM in a package envelope of 1.090 x 1.090 x 0.300 inches. The DPS128C32BV3 contains four individual 128K x 8 SRAMs, packaged in their own hermetically sealed SLCCs making the module suitable for commercial, industrial and military applications.DESCRIPTION
: By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or hybrid techniques. w w w PIN-OUT DIAGRAM * Commercial only. .D at PIN NAMES A0 - A16 I/O0 - I/O31 CE0 - CE3 WE0 - WE3 OE VDD VSS N.C. aS he Address Inputs Data Input/Output Chip Enables Write Enables Output Enable Power (+5V) Ground No Connect 30A044-28 REV. F et 4U This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 .c omFEATURES
:● Organizations Available: 128K x 32, 256K x 16, or 512K x 8
● Access Times: 20, 25, 30, 35, 45ns
● Fully Static Operation - No clock or refresh required
● Single +5V Power Supply, ±10% Tolerance
● TTL Compatible
● Common Data Inputs and Outputs
● Low Data Retention Voltage: 2.0V min.
● 66-Pin PGA ‘’VERSA-STACK’’ Package FUNCTIONAL BLOCK DIAGRAM DPS128C32BV3 RECOMMENDED OPERATING RANGE 3 Symbol Characteristic Min.