P2V64S40ETP Datasheet PDF - Deutron Electronics 64Mb Synchronous DRAM Specs

P2V64S40ETP - 64Mb Synchronous DRAM

Datasheet Summary

Description

The P2V64S40ETP is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits.

Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle.

Features

3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) Pin Configurations.
All inputs are sampled at the positive going edge of the system clock.
Auto & self refresh.
64ms refresh period (4K cycle).
Burst read single write operation.
LDQM & UDQM for m.

Datasheet Details

Part number	P2V64S40ETP
Manufacturer	Deutron Electronics
File Size	676.03 KB
Description	64Mb Synchronous DRAM
Datasheet	P2V64S40ETP Datasheet
Additional preview pages of the P2V64S40ETP datasheet.

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64Mb Synchronous DRAM Specification P2V64S40ETP Deutron Electronics Corp. 8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104, TAIWAN, R. O. C. TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 64Mb Synchronous DRAM P2V64S40ETP (4-bank x 1,048,576-word x 16-bit) General Description The P2V64S40ETP is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features • 3.

Published: Mar 7, 2016 |