P3P4GF4BLF - 4G Bits Die DDRIII SDRAM

Key Features

Double-data-rate architecture: two data transfers per clock cycle.
The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transitions.
Commands ent.

P3P4GF4BLF 4g bits die ddriii sdram by Deutron Electronics - Datasheet Preview

Datasheet Details

Part number	P3P4GF4BLF
Manufacturer	Deutron Electronics
File Size	2.19 MB
Description	4G Bits Die DDRIII SDRAM
Datasheet	P3P4GF4BLF Datasheet

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Full PDF Text Transcription (Reference)

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4G B Die DDRIII SDRAM Specification P3P4GF4BLF Deutron Electronics Corp. 8F, 68, Sec. 3, NanKing E. RD., Taipei 104, Taiwan, R.O.C. TEL: (886)-2-2517-7768 FAX: (886)-2-2517-4575 P3P4GF4BLF (256M words x 16 bits) Specifications  Density: 4G bits  Organization  32M words  16 bits  8 banks  Package  96-ball FBGA  Lead-free (RoHS compliant) and Halogen-free  Power supply: VDD, VDDQ  1.5V  0.075V  Data rate  1600Mbps/1333Mbps/1066Mbps (max.