P3R1GE4JGF - 1G bits DDR2 SDRAM

This page provides the datasheet information for the P3R1GE4JGF, a member of the P3R1GE3JGF 1G bits DDR2 SDRAM family.

Features

Double-data-rate architecture; two data transfers per clock cycle.
The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture.
Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver.
DQS is edge-aligned with data for READs; centeraligned with data for WRITEs.
Differential clock inputs (CK and /CK).
DLL aligns DQ and DQS transitions with CK transi.

P3R1GE4JGF 1G bits DDR2 SDRAM by Deutron Electronics - Datasheet Preview — Datasheet preview – P3R1GE4JGF

Datasheet Details

Part number	P3R1GE4JGF
Manufacturer	Deutron Electronics
File Size	2.91 MB
Description	1G bits DDR2 SDRAM
Datasheet	P3R1GE4JGF Datasheet
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P3R1GE3JGF - 1G bits DDR2 SDRAM

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DATA SHEET 1G bits DDR2 SDRAM P3R1GE3JGF(128M words × 8 bits) P3R1GE4JGF(64M words × 16 bits) Specifications • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (P3R1GE3JGF)  8M words × 16 bits × 8 banks (P3R1GE4JGF) • Package  60-ball FBGA (P3R1GE3JGF)  84-ball FBGA (P3R1GE4JGF)  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Data rate  800Mbps (max.

Published: Aug 18, 2014 |