Digital Core Design DFP2INT
The DFP2INT is the pipelined floating point to integer converter. The input and output numbers format is according to IEEE-754 standard. DFP2INT supports single precision real numbers and double word integers (4 Bytes).| Part No. | DFP2INT |
|---|---|
| Datasheet | DFP2INT Download |
| Manufacturer |  Digital Core Design |
| Description | Floating Point To Integer Pipelined Converter |
| Buy | Stock & Price |
FEATURES
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● Full IEEE-754 compliance Single precision real input numbers Double word output numbers(4 Bytes) Simple interface No programming required 2 levels pipelining Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implementation. It also permits FPGA prototyping before ASIC production. All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
