Digital Core Design DFPSQRT
The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is according to IEEE-754 standard. DFPSQRT supports single precision real numbers.| Part No. | DFPSQRT |
|---|---|
| Datasheet | DFPSQRT Download |
| Manufacturer |  Digital Core Design |
| Description | Floating Point Pipelined Square Root Unit |
| Buy | Stock & Price |
FEATURES
●●
●
●
●
●
●
● Full IEEE-754 compliance Single precision real format support Simple interface No programming required 9 levels pipelining 24-bit accuracy, 6 fractional decimal digits Results available at every clock Fully configurable Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows using IP Core in single FPGA bitstream and ASIC implemenhttp:// All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. tation. It also permits FPGA prototyping before ASIC production. Unlimited Designs license allows using IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
