DZ80 Datasheet | Digital Core Design

OVERVIEW Document contains brief description of DZ80 core functionality. The DZ80 is an advanced 8bit microprocessor with 208 bits of user accessible registers, posed of six general purpose registers, able to be used individually as either 8-bit registers, or as 16-bit register pairs. Additionally to those registers, DZ80 supports two sets of accumulator and flag registers. The DZ80 contains also Stack Pointer, program Counter, two index registers, a REFRESH register, and an INTERRUPT register. All output signals are fully decoded and timed to control standard memory or peripheral circuits. The DZ80 is supported by a wide range of peripherals family. DZ80 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with plete set of tests allowing easy package validation at each stage of So C design flow. - - - - - - CPU FEATURES Fully patible with industry standard Z80 Fully synthesizable, static synchronous design with no internal tri-states No internal reset generator or gated clock Scan test ready Technology independent HDL source code Core can be fully customized DESIGN FEATURES - - - - ONE GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE ALL LATHES IMPLEMENTED IN ORIGINAL Z80 MICROCONTROLLER ARE REPLACED BY EQUIVALENT FLI-FLOPS. All trademarks mentioned in this document are trademarks of their respective owners. http://.Digital Core Design. http://.dcd.pl Copyright 1999-2006 DCD - Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF - VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ Model Sim automatic simulation macros ◊ Tests with reference responses - Technical documentation ◊ Installation notes ◊ HDL core specification...