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74AUP1G86FS3-7 - SINGLE 2-INPUT EXCLUSIVE-OR GATE

Download the 74AUP1G86FS3-7 datasheet PDF. This datasheet also covers the 74AUP1G86 variant, as both devices belong to the same single 2-input exclusive-or gate family and are provided as variant models within a single manufacturer datasheet.

General Description

The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications.

Key Features

  • Advanced Ultra Low Power (AUP) CMOS.
  • Supply Voltage Range from 0.8V to 3.6V.
  • ± 4mA Output Drive at 3.0V.
  • Low Static Power Consumption ICC < 0.9µA.
  • Low Dynamic Power Consumption CPD = 6.3pF (Typical at 3.6V).
  • Schmitt Trigger Action at all inputs makes the circuit tolerant for slower input rise and fall time. The hysteresis is typically 250mV at VCC = 3.0V.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • ESD Protection Exce.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74AUP1G86-Diodes.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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74AUP1G80 Low-power D-type flip-flop nexperia
74AUP1G885 Low Power Dual Function Gate NXP

Other Datasheets by Diodes Incorporated

Part Number Description
74AUP1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE
74AUP1G00 SINGLE 2 INPUT POSITIVE NAND GATE
74AUP1G02 SINGLE 2 INPUT POSITIVE NOR GATE
74AUP1G04 SINGLE INVERTER GATE
74AUP1G06 SINGLE INVERTER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74AUP1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE Description The Advanced, Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. Pin Assignments The 74AUP1G86 is a single, two-input, positive exclusive-OR gate with a standard push-pull output designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging current backflow when the device is powered down. The gate performs the positive Boolean function: Y = A ⊕ B or Y = AB + A B Features • Advanced Ultra Low Power (AUP) CMOS • Supply Voltage Range from 0.8V to 3.6V • ± 4mA Output Drive at 3.0V • Low Static Power Consumption ICC < 0.