74AUP2G125 Description
Pin Assignments The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G125 is a dual 3-State Buffer. Each buffer has an individual output enable pin while asserted HIGH will place the output in a high impedance state.
74AUP2G125 Key Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8 V to 3.6 V
- ± 4 mA Output Drive at 3.0 V
- Low Static Power Consumption
- Icc < 0.9 uA
- Low Dynamic Power Consumption
- CPD = 6 pF Typical at 3.6 V