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74LVC1G125 - SINGLE BUFFER GATE

General Description

The 74LVC1G125 is a single, non-inverting buffer/bus driver with a 3-state output.

The output enters a high-impedance state when a HIGH-level is applied to the output enable (OE) pin.

The device is designed for operation with a power supply range of 1.65V to 5.5V.

Key Features

  • Wide Supply Voltage Range from 1.65 to 5.5V.
  • ± 24mA Output Drive at 3.3V.
  • CMOS Low Power Consumption.
  • IOFF Supports Partial-Power-Down Mode Operation.
  • Inputs Accept Up to 5.5V.
  • ESD Protection Tested per JESD 22.
  • Exceeds 200-V Machine Model (A115).
  • Exceeds 2000-V Human Body Model (A114).
  • Exceeds 1000-V Charged Device Model (C101).
  • Latch-Up Exceeds 100mA per JESD 78, Class I.
  • Range of Package Options.
  • Direct Interface with TTL Levels.

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Other Datasheets by Diodes Incorporated

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74LVC1G126 SINGLE BUFFER GATE
74LVC1G10 SINGLE 3 INPUT POSITIVE NAND GATE
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74LVC1G125 SINGLE BUFFER GATE WITH 3-STATE OUTPUT Description The 74LVC1G125 is a single, non-inverting buffer/bus driver with a 3-state output. The output enters a high-impedance state when a HIGH-level is applied to the output enable (OE) pin. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V, allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down. Features  Wide Supply Voltage Range from 1.65 to 5.5V  ± 24mA Output Drive at 3.3V  CMOS Low Power Consumption  IOFF Supports Partial-Power-Down Mode Operation  Inputs Accept Up to 5.