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DMP1012UCB9 - P-Channel MOSFET

General Description

This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer.

It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area.

Key Features

  • LD-MOS Technology with the Lowest Figure of Merit: RDS(on) = 8.2mΩ to Minimize On-State Losses Qg = 8.1nC for Ultra-Fast Switching.
  • Vgs(th) = -0.8V typ. for a Low Turn-On Potential.
  • CSP with Footprint 1.5mm × 1.5mm.
  • Height = 0.62mm for Low Profile.
  • ESD = 6kV HBM Protection of Gate.
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2).
  • Halogen and Antimony Free. “Green” Device (Note 3).
  • Qualified to AEC-Q101 Standards for.

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Full PDF Text Transcription for DMP1012UCB9 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DMP1012UCB9. For precise diagrams, and layout, please refer to the original PDF.

NEW PRODUCT AADDVVAANNCCEED IINNFFOORRMMAATTIIOONN DMP1012UCB9 P-CHANNEL ENHANCEMENT MODE MOSFET Product Summary (Typ. @ VGS = -4.5V, TA = +25°C) VDSS -8V RDS(on) 8.2mΩ Q...

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duct Summary (Typ. @ VGS = -4.5V, TA = +25°C) VDSS -8V RDS(on) 8.2mΩ Qg 8.1nC Qgd 1.8nC ID -10A Description This 3rd generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. It uses Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area. Features • LD-MOS Technology with the Lowest Figure of Merit: RDS(on) = 8.2mΩ to Minimize On-State Losses Qg = 8.1nC for Ultra-Fast Switching • Vgs(th) = -0.8V typ. for a Low Turn-On Potential • CSP with Footprint 1.5mm × 1.5m

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