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DMP1018UCB9 - P-Channel MOSFET

General Description

This 1st generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer.

Using Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area.

Key Features

  • LD-MOS technology with the lowest Figure of Merit: RDS(on) = 12mΩ to Minimize On-State Losses Qg = 4.9nC for Ultra-Fast Switching.
  • Vgs(th) = -0.8V typ. for a Low Turn-On Potential.
  • CSP with Footprint 1.5mm × 1.5mm.
  • Height = 0.62mm for Low Profile.
  • ESD = 3kV HBM Protection of Gate.
  • Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2).
  • Halogen and Antimony Free. “Green” Device (Note 3).
  • Qualified to AEC-Q101 Standards for High Reliability Mechanical Data.

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Full PDF Text Transcription for DMP1018UCB9 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DMP1018UCB9. For precise diagrams, and layout, please refer to the original PDF.

AADDVVAANNCCEED ININENFFWOORPRRMMOAADTTIUIOCONTN Product Summary VDSS -12V RDS(on) 12mΩ Qg 4.9nC Qgd 1.1nC ID -7.6A Typ. @ VGS = -4.5V, TA = +25°C Description This 1st ge...

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1.1nC ID -7.6A Typ. @ VGS = -4.5V, TA = +25°C Description This 1st generation Lateral MOSFET (LD-MOS) is engineered to minimize on-state losses and switch ultra-fast, making it ideal for high efficiency power transfer. Using Chip-Scale Package (CSP) to increase power density by combining low thermal impedance with minimal RDS(on) per footprint area. Applications  DC-DC Converters  Battery Management  Load Switch DMP1018UCB9 P-CHANNEL ENHANCEMENT MODE MOSFET Features  LD-MOS technology with the lowest Figure of Merit: RDS(on) = 12mΩ to Minimize On-State Losses Qg = 4.9nC for Ultra-Fast Switching  Vgs(th) = -0.8V typ.

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