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DL5064 - (DL5500 Series) The Industry's First Fast Field Programmable Gate Array

This page provides the datasheet information for the DL5064, a member of the DL5500 (DL5500 Series) The Industry's First Fast Field Programmable Gate Array family.

Description

.

10 Logic Blocks

Features

  • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns ECL, PECL and GTL Interface Levels 100K and 100KH Compatible Differential Outputs 1,000 to 10,000 Gates 6 Low-skew Clock Trees Highly Predictable, Fanout Independent Routing Delays.
  • SRAM-based Programming.
  • JTAG Boundary Scan.
  • Fully Automa.

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Datasheet preview – DL5064

Datasheet Details

Part number DL5064
Manufacturer DynaChip
File Size 567.09 KB
Description (DL5500 Series) The Industry's First Fast Field Programmable Gate Array
Datasheet download datasheet DL5064 Datasheet
Additional preview pages of the DL5064 datasheet.

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Full PDF Text Transcription

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DL5000™ Family Fast Field Programmable Gate Array Features • Fast Field Programmable Gate Arrays™ Patented Active Repeater™ Architecture Data and Clock Rates up to 270 MHz Complex operations up to 200 MHz Input Block Register Setup Time 800 ps Output Block Register Clock-to-out 1.6 ns ECL, PECL and GTL Interface Levels 100K and 100KH Compatible Differential Outputs 1,000 to 10,000 Gates 6 Low-skew Clock Trees Highly Predictable, Fanout Independent Routing Delays • SRAM-based Programming • JTAG Boundary Scan • Fully Automatic Implementation Using DynaTool™ • • • • • • • • • • • DL5 2 PG 20 56 964 1 8 Introduction The DL5000 is the industry’s first Fast Field Programmable Gate Array (FFPGA™) family.
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