M13S128324A

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

M13S128324A datasheet by ESMT (Elite Semiconductor Microelectronics Technology).

M13S128324A Datasheet Details

Part number	M13S128324A
Datasheet	M13S128324A-ESMT.pdf
File Size	1.72 MB
Manufacturer	ESMT (Elite Semiconductor Microelectronics Technology)
Description	Double Data Rate SDRAM

Pin Name Function Pin Name Function A0~A11, BA0,BA1 Address inputs - Row address A0~A11 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1.

Double-data-rate architecture, two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CLK and CLK )
DLL aligns DQ and DQS transition with CLK transition
Quad bank operation
CAS Latency : 2, 2.5, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8
All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
Data I/O transitions on both edges of data strobe (DQS)

Part Number	Description
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M13S128168A-4.5TG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-4BG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-4TG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5BG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S128168A-5TG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
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M13S128168A-6TG2S	2M x 16 Bit x 4 Banks Double Data Rate SDRAM
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