M14D1G1664A-2.5BG2S Overview
ESMT DDR II SDRAM M14D1G1664A (2S) 8M x 16 Bit x 8 Banks DDR II SDRAM.
M14D1G1664A-2.5BG2S Key Features
- JEDEC Standard
- VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
- Internal pipelined double-data-rate architecture; two data access per clock cycle
- Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation
- On-chip DLL
- Differential clock inputs (CLK and CLK )
- DLL aligns DQ and DQS transition with CLK transition
- 8 bank operation
- CAS Latency : 3, 4, 5, 6, 7
- Additive Latency: 0, 1, 2, 3, 4, 5, 6