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M14F2561616A Key Features

  • JEDEC Standard
  • VDD / VDDQ = 1.5V ± 0.075V
  • Internal pipelined double-data-rate architecture; two data access per clock cycle
  • Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation
  • On-chip DLL
  • Differential clock inputs (CLK and CLK )
  • DLL aligns DQ and DQS transition with CLK transition
  • 1KB page size
  • Row address: A0 to A12
  • Column address: A0 to A8

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M14F2561616A Description

Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out mand input mand input mand input Ground Power Bi-directional differential Data Strobe. LDQS and LDQS are DQS for DQ0~DQ7;.