Datasheet Details
| Part number | M15T5121632A-DEBG |
|---|---|
| Manufacturer | ESMT (Elite Semiconductor Microelectronics Technology) |
| File Size | 7.24 MB |
| Description | 4M x 16-Bit x 8 Banks DDR3 SDRAM |
| Datasheet |
 M15T5121632A-DEBG Datasheet
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General Description
The 512Mb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight-bank DRAM.
The 512Mb chip is organized as 4Mbit x 16 I/Os x 8 bank devices.
Key Features
- and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 32Mb x 16 # of Bank 8 Bank Address BA0.