M52S32321A
Key Features
- LVCMOS compatible with multiplexed address
- Dual banks operation
- MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
- EMRS cycle with address key programs
- All inputs are sampled at the positive going edge of the system clock
- Burst Read Single-bit Write operation
- Special Function Support
