M53D5121632A-7.5BG Overview
Key Features
- JEDEC Standard
- Internal pipelined double-data-rate architecture, two data access per clock cycle
- Bi-directional data strobe (DQS)
- No DLL; CLK to DQS is not synchronized
- Differential clock inputs (CLK and CLK )
- Four bank operation
- CAS Latency : 2, 3
- Burst Type : Sequential and Interleave
- Special function support
- PASR (Partial Array Self Refresh)
