M55D1G3232A-GFBG2Y
M55D1G3232A-GFBG2Y is 4M x 32 Bit x 8 Banks LPDDR3 SDRAM manufactured by Elite Semiconductor Microelectronics Technology.
Feature
- Ultra-low-voltage core and I/O power supplies VDD1 = 1.70- 1.95V VDD2, VDDCA, VDDQ = 1.14- 1.30V
- Organization 4M words x 32 bits x 8 banks
- JEDEC LPDDR3-pliant
- 4KB page size
Row address: R0-R12 Column address: C0-C8 (x32 bits)
- Auto precharge option for each burst access
- Eight-bit prefetch DDR architecture
- Eight internal banks for concurrent operation
- Double data rate, mand/address inputs; mands entered on each CK edge
- Bidirectional/differential data strobe per byte of data (DQS)
- Differential clock inputs (CK_t and CK_c)
- Data mask (DM) for write data
M55D1G3232A (2Y)
4M x 32 Bit x 8 Banks LPDDR3 SDRAM
- mand/Address (CA) training for CA input timing adjustment
- Write leveling for clock to DQ, DQS, and DM timing adjustment
- Interface: HSUL_12
- Read latency (RL): 3, 6, 8, 9, 10, 11, 12, 14, 16
- Burst length (BL): 8
- Burst type (BT): Sequential
- Per-bank refresh for concurrent operation
- Auto temperature pensated self refresh (ATCSR)
- Auto refresh and self refresh
- Refresh cycles: 4,096 cycles/32ms
Average refresh period: 7.8μs
- Partial-array self refresh (PASR)
Bank masking Segment masking
- Deep power-down (DPD)
- Programmable drive strength (DS)
- On-die termination (ODT)
Ordering Information
Product ID
Max Freq. Data Rate
(MHz) (Mb/s/pin)
M55D1G3232A-EEBG2Y
M55D1G3232A-CDBG2Y...
