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M56Z4G32128A-SMBYG2R - 16M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM

General Description

19 General Notes19 MR0, MR[6:5], MR8, MR13, MR24 Definition 20 IDD Parameters21 Functional Description 25 Monolithic Device Addressing 26 Simplified Bus Interface State Diagram 27 Power-Up and Initialization 29 Voltage Ramp30 Reset Initialization with Stable Power32 Power-Off Sequence33 Controlled P

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M56Z4G32128A-TNBYG2R 16M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z4G16256A-SMBYG2H 32M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z4G16256A-TNBYG2H 32M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z2G16128A-SMBYG2R 16M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM
M56Z2G16128A-TNBYG2R 16M x 16 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ESMT M56Z4G32128A (2R) LPDDR4/LPDDR4X SDRAM 16M x 32 Bit x 8 Banks LPDDR4/LPDDR4X SDRAM Feature  Ultra-low-voltage core and I/O power supply – VDD1 = 1.70–1.95V; 1.80V nominal – VDD2 = 1.06–1.17V; 1.10V nominal – VDDQ = 1.06–1.17V; 1.10V nominal or Low VDDQ = 0.57–0.65V; 0.60V nominal  Array configuration – 128 Meg × 32 (2 channels ×16 I/O)  Device configuration – 128M16 × 2 die in package  16n prefetch DDR architecture  8 internal banks per channel for concurrent operation  Single-data-rate CMD/ADR entry  Bidirectional/differential data strobe per byte lane  Programmable READ and WRITE latencies (RL/WL)  Programmable and on-the-fly burst lengths (BL = 16, 32)  Directed per-bank refresh for concurrent bank operation and ease of command scheduling  Up to 8.