AN983B
Overview
Draft data sheet for review First release Add 28 MRXCK Add 26 PMEP Add 27 PMEPEN Sep, 2001 Sep, 2001 Sep, 2001 1.2 1.3 1.4 Add 25MHz crystal accuracy Revise PHY registers Revise product logo of Pin assignment diagram P.17 MrxD0~D3 P.23 CIOSA : 1 means enable ; 0 means disable P.14 Add LED info to pin diagram JULY, 2002 1.5 P.25 Offset 80h, DID default value : 0981h P.40 CSR18[25] / PWRS_clr : 1 means PCI_reset rising will clear CR49[1:0]/PWRS JULY, 2002 JULY, 2002 MAY, 2003 1.6 1.7 1.8 P.85 FIG21, FIG22, FIG23, FIG24 added for MII interface signal timing. P.45 Unicast registers added P.69 Modify some error statement about Loop-back Operation of transceiver.
- 1 1.0 1.1 PCI/miPCI Fast Ethernet Controller with integrated PHY
