AS4LC8M8S0 Datasheet PDF (3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM)

AS4LC8M8S0 - 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

Description

Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable AS4LC4M16S0 Selection guide Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold

Features

PC100/133 compliant.
Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16).
Fully synchronous - All signals referenced to positive edge of clock.
Four internal banks controlled by BA0/BA1 (bank select).
High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time.
Low power consumption - Standby: 7.2 mW max, CMOS I/O.
4096 refresh cycles, 64 ms refresh interva.

Datasheet Details

Part number	AS4LC8M8S0
Manufacturer	ETC
File Size	566.21 KB
Description	3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
Datasheet	AS4LC8M8S0 Datasheet
Additional preview pages of the AS4LC8M8S0 datasheet.

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Full PDF Text Transcription

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Advance information ® AS4LC8M8S0 AS4LC4M16S0 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM Features • PC100/133 compliant • Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) • Fully synchronous - All signals referenced to positive edge of clock • Four internal banks controlled by BA0/BA1 (bank select) • High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time • Low power consumption - Standby: 7.2 mW max, CMOS I/O • 4096 refresh cycles, 64 ms refresh interval • Auto refresh and self refresh • Automatic and direct precharge • Burst read, single write operation • Can assert random column address in every cycle • LVTTL compatible I/O • 3.

Published: Mar 24, 2005 |