AS4LC8M8S0 Overview
Output disable/write mask Address inputs Bank select inputs Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V ± 0.3V) Ground Clock input Clock enable AS4LC4M16S0 Selection guide Symbol Bus frequency Minimum clock access time Minimum setup time Minimum hold time Minimum RAS to CAS delay Minimum RAS precharge time Remarks: Very high bandwidth is achieved using a pipelined...
AS4LC8M8S0 Key Features
- PC100/133 pliant
- Organization
- 2,097,152 words × 8 bits × 4 banks (8M×8)
- 1,048,576 words × 16 bits × 4 banks (4M×16)
- Fully synchronous
- All signals referenced to positive edge of clock
- Four internal banks controlled by BA0/BA1 (bank select)
- High speed
- 133/125/100 MHz
- 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time