Description
Pin Number 1
2 3 4 5 6 7 8
9
10 11 12 13 14
15 16
Symbol A
VO RR1 RC1 RC2 RR2 Vss VRF
VC
IB Vdd 2OUT 2IN1IN+
1IN1OUT
Description
Retriggerable & non-retriggerable mode select
(A=1 : re-triggerable)
Detector output pin (active high)
Output pulse width control (Tx)
See definition below
Output pulse width control (Tx)
Trigger inhibit control (Ti)
Trigger inhibit control (Ti)
Ground
RESET & voltage reference input
(Normally high.Low=reset)
Trigger disable inp
Features
- Low power CMOS technology (ideal for battery operated PIR devices) CMOS high input impedance operational amplifiers Bi-directional level detector / Excellent noise immunity Built-in Power up disable & output pulse control logic Dual mode : retriggerable & non-retriggerable
Pin.
BISS0001 Datasheet
