Overview: .. Bt8110/8110B
High-Capacity ADPCM Processor
This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation (ADPCM) encoding and decoding. The fixed-rate coding algorithms include those specified in ANSI Standard T1.303-1989. These algorithms are identical to those in ITU-T Remendations G.726 and G.727. These circuits also implement the variable-rate or embedded codes specified in ANSI Standard T1.310-1991 and ITU-T Remendation G.727. A single ADPCM processor integrated circuit can provide 24 or 32 full-duplex channels of ADPCM processing (encoding and decoding). In some applications, two circuits can be bined to provide 48 or 64 full-duplex channels. Both A-law and µ-law PCM translations are provided. Interface options such as serial and parallel inputs and outputs, along with hardware and microprocessor control modes, are provided by the integrated circuits. Up to 14 separate ADPCM algorithms are available in any given configuration on a per-channel basis. The Bt8110 requires an external lookup table ROM. The Bt8110B has an internal lookup table ROM, or can use an external lookup table ROM. When in direct framer interface mode, transparent channels in the Bt8110 will operate at 56 kbit/s; the Bt8110B operates at 64 kbit/s. A hardware control, direct framer interface mode has . been added to the Bt8110B. For more details on the Bt8110B mode controls, refer to Table 1-1 and Table 1-4.
