CY28447 Datasheet | Unknown Manufacturer

.. PRELIMINARY Clock Generator for Intel® Calistoga Chipset Features - pliant to Intel® CK410M - Selectable CPU frequencies - Differential CPU clock pairs - 100 MHz differential SRC clocks - 96 MHz differential dot clock - 27 MHz Spread and Non-spread video clock - 48 MHz USB clock - SRC clocks independently stoppable through CLKREQ#[1:9] - 96/100 MHz spreadable differential video clock CPU x2 / x3 SRC x9/11 PCI x5 REF x2 DOT96 x1 USB_48M x1 LCD x1 27M x2 - 33 MHz PCI clocks - Buffered Reference Clock 14.318MHz - Low-voltage frequency select inputs - I2C support with readback capabilities - Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction - 3.3V power supply - 72-pin QFN package Block Diagram XIN XOUT SEL_CLKREQ PCI_STP# CPU_STP# CLKREQ[1:9]# ITP_SEL FS[C:A] 14.318M Hz Crystal VDD REF[1:0] IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT10 CPUC2_ITP/SRCC10 VDD SRCT(1:9]) SRCC(1:9]) VDD PCI[1:4] VDD_PCI PCIF0 VDD SRCT0/100M T_SST SRCC0/100M C_SST VDD48 27MSpread VDD48 DOT96T DOT96C VDD48 48M 27M PLL VTT_PW RGD#/PD SDATA SCLK I2C Logic Pin Configuration CLKREQ9# CLKREQ8# SRCT_8 SRCC_8 VSS_SRC SRCC_7 SRCT_7 VDD_SRC SRCC_6 SRCT_6 CLKREQ6# SCRC_5 SRCT_5 SCRC_4 SRCT_4 CLKREQ4# SRCC_3 SRCT_3 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 PLL Reference CPU PLL Divider LVDS PLL...