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DDU4C - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)

Description

The DDU4C-series device is a 5-tap digitally buffered delay line.

The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table).

The total delay of the line is measured from IN to T5.

Features

  • Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 2 10 T L fan-out capability IN 1 14 12 T2 T4 GND 4 10 6 7 8 data 3 ® delay devices, inc.

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Datasheet preview – DDU4C

Datasheet Details

Part number DDU4C
Manufacturer ETC
File Size 65.50 KB
Description 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
Datasheet download datasheet DDU4C Datasheet
Additional preview pages of the DDU4C datasheet.

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Other Datasheets by ETC
  • DDU4C-5050 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5060 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5075 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5100 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5125 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5150 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5200 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)
  • DDU4C-5250 - 5-TAP/ HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C)

Full PDF Text Transcription

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DDU4C 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) FEATURES • • • • • • Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully CMOS interfaced & buffered 2 10 T L fan-out capability IN 1 14 12 T2 T4 GND 4 10 6 7 8 data 3 ® delay devices, inc. PACKAGES VCC T1 T3 T5 IN N/C N/C T2 N/C T4 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD N/C T1 N/C T3 N/C T5 DIP DDU4C-xx Comm. DDU4C-xxM Military SMD DDU4C-xxA2 Comm. DDU4C-xxB2 Comm. DDU4C-xxMC2 Military FUNCTIONAL DESCRIPTION The DDU4C-series device is a 5-tap digitally buffered delay line. The signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an amount determined by the device dash number (See Table).
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