EPA018BV Datasheet | Unknown Manufacturer

Excelics DATA SHEET High Efficiency Heterojunction Power FET - - - - - - - - VERY HIGH fmax: 120GHz +20.0d Bm TYPICAL OUTPUT POWER 13.0d B TYPICAL POWER GAIN AT 18 GHz TYPICAL 0.75d B NOISE FIGURE AND 12.5d B ASSOCIATED GAIN AT 12GHz 0.3 X 180 MICRON RECESSED “MUSHROOM” GATE Si3N4 PASSIVATION AND VIA HOLE GROUNDING ADVANCED EPITAXIAL HETEROJUNCTION PROFILE PROVIDES EXTRA HIGH POWER EFFICIENCY, AND HIGH RELIABILITY Idss SORTED IN 5 m A PER BIN RANGE : Via Hole Chip Thickness: 75 ± 13 microns All Dimensions In Microns ELECTRICAL CHARACTERISTICS (Ta = 25 OC) SYMBOLS P1d B G1d B PAE NF Ga Idss Gm Vp BVgd BVgs Rth PARAMETERS/TEST CONDITIONS Output Power at 1d B pression f=12GHz Vds=6V, Ids=50% Idss f=18GHz Gain at 1d B pression f=12GHz Vds=6V, Ids=50% Idss f=18GHz Power Added Efficiency at 1d B pression Vds=6V, Ids=50% Idss f=12Ghz Noise Figure f=12GHz Vds=2V, Ids=15m A Associated Gain f=12GHz Vds=2V, Ids=15m A Saturated Drain Current Transconductance Pinch-off Voltage Drain Breakdown Voltage Source Breakdown Voltage Vds=3V, Vgs=0V Vds=3V, Vgs=0V Vds=3V, Ids=1.0m A Igd=0.5m A Igs=0.5m A -9 -7 MIN 18.0 13.0 TYP 20.0- 20.0- 14.5 13.0 48 0.75 12.5 30 35 55 60 -1.0 -15 -14 140 o UNIT d Bm d B % d B d B 80 m A m S -2.5 V V V C/W Thermal Resistance (Au-Sn Eutectic Attach) - P1d B = 21.5d Bm can be obtained with 8v/50% Idss bias. Consult factory for wafer selection. MAXIMUM RATINGS AT 25OC SYMBOLS Vds Vgs Ids Igsf Pin Tch Tstg Pt PARAMETERS Drain-Source Voltage Gate-Source Voltage Drain Current Forward Gate Current Input Power Channel Temperature Storage Temperature Total Power Dissipation ABSOLUTE1 12V -8V Idss 9m A 16d Bm 175o C -65/175o C 950m W CONTINUOUS2 6V -3V Idss 1.5m A @3d B pression 150o C -65/150o C 800m W Note: 1. Exceeding any of the above ratings may result in permanent damage. 2. Exceeding any of the above ratings may reduce MTTF below design goals. Excelics Semiconductor, Inc., 2908 Scott Blvd., Santa Clara, CA 95054 Phone: (408) 970-8664 Fax: (408) 970-8998 Web...